1. Field of the Invention
The present invention relates to an integrated circuit structure and fabrication method thereof. More specifically, the present invention relates to an integrated circuit including a pass-gate constructed using transistors that are stacked perpendicular to a substrate surface.
2. Description of the Related Art
The primary goal of integrated circuit fabrication is the production of circuits having the highest performance at the lowest cost. The main performance criteria for MOS integrated circuits are speed, power dissipation, and device packing density. The goals of improving performance and reducing cost have been mainly achieved through reductions in device size. Smaller devices advantageously decrease semiconductor die size so that more chips are produced per wafer and a lower percentage of the chips on a wafer are unusable, thus reducing the die cost.
Accordingly, the semiconductor industry has focused on reducing device size for generating technological advancements. However, the reduction in device size alone, without considering other processing parameters may adversely affect integrated circuit performance. For example, power dissipation may degrade because of an increase in device leakage currents or circuit speed may degrade when device sizes are reduced. Reliability problems affecting submicron MOSFETs may also be exacerbated, resulting in hot-carrier degradation, wearing of gate oxide, and electromigration.
What is needed is sophisticated design techniques and design structures that reduce device sizes while maintaining electrical behavior comparable to the behavior of previous generations of larger devices.